The present invention relates to a solid-state memory device to be produced by lithography and a method for arrangements of solid-state memory cells. The solid-state memory device includes MRAM (Magnetic Random Access Memory), DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), FRAM (Ferroelectric Random Access Memory), ROM (Read Only Memory), PROM (Programmable ROM), and EPROM (Erasable and Programmable ROM). More particularly, the present invention relates to the array pattern of the information storing parts of memory elements.
The recent wide spread of information and communications equipment, particularly personal small ones such as portable terminals, requires their constituents such as memory and logic elements to have improved performance, including high integration, high speed, and low power consumption.
Especially, non-volatile memory is regarded as indispensable in the age of ubiquitous computing because it preserves important personal information in case of dead battery and network failure or server breakdown. Recent portable equipment is so designed as to reduce power consumption as much as possible by keeping idle circuit blocks in stand-by mode. It would be possible to save power and memory if high-speed, high-capacity non-volatile memory is realized. It would make the “instant-on function” feasible which permits equipment to start working instantly as soon as power is turned on.
Among non-volatile memory devices are flush memory using semiconductors, and FRAM (ferroelectric random access memory) using ferroelectric substances.
Unfortunately, flush memory is limited in writing speed to the order of microseconds. FRAM is also limited in the number of rewriting cycles to 1012 to 1014, that is, it is too poor in endurance to replace SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory). Moreover, it presents difficulties in microprocessing of ferroelectric capacitors therein.
There is a noteworthy non-volatile memory device free of these disadvantages, capable of high-speed operation with a low power consumption, and suitable for high capacity (or high degree of integration). It is a magnetic memory device called MRAM (Magnetic Random Access Memory).
MRAM in the early stage is based on the spin valve which utilizes the AMR (Anisotropic Magnetoresistive) effect or the GMR (Giant Magnetoresistance) effect. The former was reported by J. M. Daughton in “Thin Solid Films”, vol 216, pp. 162-168, 1992, and the latter was reported by D. D. Tang et al. in “IEDM Technical Digest” pp. 995-997, 1997. Unfortunately, they have the disadvantage that the memory cell has a low resistance of 10 to 100. which leads to a large power consumption per bit for reading. This disadvantage makes it difficult to realize a large-capacity memory.
There is another type of MRAM which utilizes the TMR (Tunnel Magnetoresistance) effect. It has come to attract attention because of its remarkable increase in the rate of change in resistance from 1 to 2% at room temperature (as reported by R. Meservey et al. in “Physics Reports”, vol. 238, pp. 214-217, 1994) to nearly 20% (as reported by T. Miyazaki et al. in “J. Magnetism & amp; Magnetic Material”, vol. 139, (L231), 1995).
A TMR element is composed of a magnetization free layer (memory layer) and a magnetization pinned layer, with a tunnel barrier layer interposed between these two magnetic layers. It stores information as “0” or “1” depending on whether the two magnetic layers are magnetized in the “parallel” direction or “anti-parallel” direction. The difference in the direction of magnetization changes the intensity of current flowing through the tunnel barrier, and this change permits the reading of information.
An MRAM of TMR type has TMR elements arrayed in a matrix pattern. It also has bit lines for access in the row and column directions and word lines for writing so that it records information in TMR devices. Information is written selectively in TMR devices only at the intersection of two lines. This process is based on the asteroid characteristics mentioned later.
Thus, the MRAM of TMR type is a semiconductor magnetic memory which can read information based on the magnetoresistance effect resulting from spin-dependent conduction characteristic of a nanomagnetic substance. It is a non-volatile memory that retains memory without external power supply. Because of its simple structure, it can be highly integrated with ease. It is capable of rewriting many times because it relies on the rotation of magnetic moment for recording. It is also expected to have a very high access speed. In fact, its ability to run at 100 MHz has been reported by R. Scheuerlein et al. in ISSCC Digest of Technical Papers, pp. 128-129, February 2000.
A detailed description will be given below of the MRAM of TMR type.
FIG. 6 is a perspective view showing a TMR element 10 as a memory cell of MRAM device. The TMR element 10, which is formed on a substrate 8, includes a magnetization free layer (memory layer) 2 and a magnetization pinned layer 4, with the former allowing the direction of magnetization to reverse comparatively easily and the latter keeping the direction of magnetization fixed. These two layers are formed from a ferromagnetic material such as nickel, iron, cobalt, or alloy thereof. The latter layer 4 may be a multi-layered film composed of ferromagnetic material, metal, and ferromagnetic material having the SAF (Synthetic Antiferromagnet) coupling. SAF has been reported by S. S. Parkin et al. in Physical Review Letters, 7, May, pp. 2304-2307 (1990).
The magnetization pinned layer 4 is in contact with the antiferromagnetic layer 5. These two layers produce an exchange interaction, which imparts strong magnetic anisotropy to the magnetization pinned layer 4. The antiferromagnetic layer 5 is formed from a manganese alloy of iron, nickel, platinum, iridium, or rhodium, or an oxide of cobalt or nickel.
The magnetization free layer (memory layer) 2 has the axis of easy magnetization (or the axis along which the ferromagnetic material is easily magnetized) which is parallel to the direction of magnetization of the magnetization pinned layer 4. Therefore, it is magnetized easily in the direction parallel or antiparallel to the direction of magnetization of the magnetization pinned layer 4, so that the direction of magnetization is easily reversed between these two states. Consequently, the magnetization free layer (memory layer) 2 can be used as an information storage medium if its two states of magnetization (“parallel” and “antiparallel” to the direction of magnetization of the magnetization pinned layer 4) are made to correspond to “0” and “1” representing information.
Between the magnetization free layer (memory layer) 2 and the magnetization pinned layer 4 is interposed a tunnel barrier layer 3 formed from an insulating material such as an oxide or nitride of aluminum, magnesium, or silicon. It cuts off the magnetic coupling between the two layers 2 and 4, and it also permits tunnel current to flow in response to the direction of magnetization of the layer 2. The magnetic layer and the conducting layer constituting the TMR element 10 are formed mainly by sputtering. The tunnel barrier layer 3 may be formed by oxidizing or nitriding the metal film which has been formed by sputtering.
The top coat layer 1 prevents mutual diffusion between the TMR element 10 and the wiring connected thereto. It also reduces contact resistance and protects the magnetization free layer (memory layer) 2 from oxidation. It is usually formed from copper, tantalum, titanium, or titanium nitride. The leading electrode layer 6 serves as a connection between the TMR element and a switching element connected thereto in series. This leading electrode layer 6 may function also as the antiferromagnetic layer 5.
FIG. 7 is a partly simplified, enlarged perspective view showing the memory of ordinary MRAM, with reading circuits omitted for brevity. This MRAM has nine memory cells and mutually intersecting bit lines 11 and writing word lines 12. Each TMR element 10 is placed at the point of intersection.
FIGS. 8 and 9 are equivalent circuit diagrams of MRAM. FIG. 8 shows the entire structure and FIG. 9 is a partly enlarged view. FIG. 9 shows six memory cells for illustration. At each point of intersection of the bit line 11 and the writing word line 12 are arranged a TMR element 10 and a field effect transistor 15 connected thereto in series. The field effect transistor 15 selects a desired element from which information is read. In addition, there are word lines 13 for reading which control ON and OFF of the field effect transistor 15 and sense lines 14 for output of read information. In the peripheral circuits, the bit lines 11 are connected to the bit line current driving circuit 16, and the word lines 12 are connected to the bidirectionally writing word line current driving circuit 17. The sense lines 14 are connected to the sense amplifier 18 which detects read information.
FIG. 10 is a schematic sectional view showing one memory cell arranged in the memory part of MRAM of related art. For brevity, the interlayer insulating film 40 is shown with its boundary and hatching omitted. (The same shall apply hereinafter.)
Above the memory cell are arranged the TMR element 10, the bit line 11, and the writing word line 12, which have been mentioned above. The bit line 11, which is formed on the TMR element 10, is electrically connected to the top coat layer 1. The writing word line 12 is formed under the TMR element 10, with an insulating layer interposed between them.
Under the memory cell is the p-type silicon semiconductor substrate 20 which has the p-type well region 21. In the well region 21 is formed the n-type MOS field effect transistor 15 including the drain electrode 23, the drain region 24, the gate electrode 13, the gate insulating film 25, the source region 26, and the source electrode 27. The gate electrode 13 of the transistor 15 is a long strip connecting cells, so that it serves also as the reading word line 13. The drain electrode 23 is connected to the leading electrode layer 6 of the TMR element 10 through the leading wiring 7, the reading connecting plugs 30 and 32, and the reading landing pads 31 and 33. The source electrode 27 is connected to the sense line 14. (In the following figures, the connecting plug is abbreviated as plug and the landing pad is abbreviated as land.) According to the example shown here, the leading wiring 7 is connected to the reading landing pad 31 through the reading connecting plug 30. However, this may be modified such that the reading connecting plug 30 is omitted and the leading wiring layer is formed directly in the connecting hole. (This shall apply hereinafter.)
The memory cell constructed as mentioned above writes information in the TMR element 10 when current is applied to the bit line 11 and the writing word line 12 in such a way that the two currents generate a combined magnetic field which magnetizes the magnetization free layer (memory layer) 2. The direction of magnetization is assigned “parallel” or “antiparallel” in response to the direction of magnetization of the magnetization pinned layer 4.
The magnetic field in the magnetization free layer (memory layer) 2 of the TMR element 10 is a vector sum of two magnetic fields HEA and HHA. The magnetic field HEA in the direction of easy axis of magnetization is induced by writing current flowing through the bit line 11. The magnetic field HHA in the direction of hard axis of magnetization is induced by writing current flowing through the writing word line 12.
Writing in MRAM is usually accomplished by applying two magnetic fields HEA (<Hs) and HHA (<Hs), either of which is not strong enough to bring about magnetization reversal, to the memory cell at the intersection of the bit line 11 and the writing word line 12 which are supplying current, so that the magnetic spin is reversed only in the memory cell on which both of the magnetic fields HEA and HHA act. This is based on the magnetization reversal indicated by the asteroid curve. Incidentally, Hs denotes the one-way reversing magnetic field. The principle of the foregoing will be detailed in the following. (Refer to U.S. Pat. No. 6,081,445.)
FIG. 11 shows an asteroid curve representing how the magnetization free layer (memory layer) 2 of the TMR element responds to magnetic fields when information is written. The asteroid curve is given by the equation below based on the condition for minimum energy.HEA2/3+HHA2/3=Hs2/3It expresses the condition for writing in the TMR element. In other words, it expresses the threshold value of the applied magnetic field which reverses the direction of magnetization of the magnetization free layer (memory layer) 2. Here, the magnitude of Hs (one-way reversing magnetic field) depends on material as well as shape of the magnetization free layer (memory layer) 2.
As shown in FIG. 11, the magnetization free layer (memory layer) 2 is acted on by the combined magnetic field H which is a vector sum of Hx and Hy, where Hx (<Hs) denotes the magnetic field HEA applied in the direction of the easy axis of magnetization and Hy (<Hs) denotes the magnetic field HHA applied in the direction of the hard axis of magnetization. Only when the combined magnetic field H is greater than the threshold value Hc corresponding to the point C on the asteroid curve and has the magnitude reaching the region 151A or 152 outside the asteroid curve, it is able to reverse the direction of magnetization of the magnetization free layer (memory layer) 2. On the other hand, when the combined magnetic field H as a vector sum remains within the region 150 of the asteroid curve, it is unable to reverse the direction of magnetization of the magnetization free layer (memory layer) 2.
The above-mentioned principle of reversing the direction of magnetization suggests that in the presence of both HEA and HHA, the magnetic field required to reverse the direction of magnetization is smaller than that which exists individually. It also suggests that if both of the bit line 11 and the writing word line 12 are used simultaneously, it is possible to write information selectively only in the TMR element 10 (memory cell) at the intersection of the two lines.
In other words, the writing current flowing through the bit line 11 applies Hx (or HEA which is the magnetic field in the direction of easy axis of magnetization) to all the TMR elements 10 arranged under the bit line 11, and the writing current flowing through the writing word line 12 applies Hy (or HHA which is the magnetic field in the direction of hard axis of magnetization) to all the TMR elements 10 arranged above the writing word line 12. However, the magnetic field which is applied individually in the direction of easy axis of magnetization or in the direction of hard axis of magnetization is smaller than the threshold value of the magnetic field for magnetization reversal. The threshold value in this case is Hs (or one-way reversing magnetic field) which is on the x axis (or easy axis of magnetization) or the y axis (or hard axis of magnetization) on the asteroid curve mentioned above. Consequently, Hx or Hy, which is smaller than Hs, cannot reverse the direction of magnetization of the magnetization free layer (memory layer) 2 so long as it is applied individually. However, at the intersection of the bit line 11 and the writing word line 12, the writing current generates the combined magnetic field H which exceeds the threshold value Hc on the asteroid curve (or which reaches the region 151(A) outside the asteroid curve). Thus the memory cell at the intersection is acted on by both Hx and Hy, and the magnetization free layer (memory layer) 2 in the memory cell has its direction of magnetization reversed.
Incidentally, if either Hx or Hy is greater than Hs (or one-way reversing magnetic field), then information is written in all the memory cells on which it acts on. Therefore, both Hx or Hy should be smaller than Hs and should not reach the region 152. The gray region 151(A) shown in FIG. 11 is the adequate region for the combined magnetic field to be applied to the magnetization free layer (memory layer) 2 for information writing.
The foregoing is applicable to a single memory cell. However, a practical magnetic memory device contains a very large number of TMR elements 10, say about one million in a 1M bit MRAM. These TMR elements slightly vary in characteristic properties from one element to another. Therefore, it is to be noted that individual elements somewhat differ in the threshold value shown in the asteroid curve and the adequate region A for the combined magnetic field to be applied for writing.
FIG. 12 is a graph showing two regions for the adequate combined magnetic fields to be applied for writing to the magnetization free layer (memory layer) 2 of two TMR elements 10 differing in the magnitude of Hs (or one-way reversing magnetic field). The symbol A1 represents the region for the adequate combined magnetic field to write information in the TMR element 10 whose one-way reversing magnetic field is Hs1. Likewise, the symbol A2 represents the region for the adequate combined magnetic field to write information in the TMR element 10 whose one-way reversing magnetic field is Hs2. Now, the combined magnetic field to be applied to write information adequately in these two TMR elements should be in the region where A1 and A2 overlap each other. If a group of memory cells include a TMR element 10 which greatly differs in Hs (or one-way reversing magnetic field), then the combined magnetic field which can correctly drive all of TMR elements 10 would be limited to a very narrow range.
FIG. 13 is a schematic sectional view illustrating how information is read from the TMR element 10. The illustrated layer structure is simplified by omitting the top coat layer 1, the antiferromagnetic layer 5, and the leading electrode layer 6.
Reading of information recorded in the TMR element 10 is accomplished by using the TMR effect which is one of the magnetoresistance effects. The TMR effect is defined as the phenomenon that resistance to tunnel current flowing from one to the other of magnetic layers facing each other through a tunnel barrier layer is small if the direction of magnetic spin of the two magnetic layers is “parallel” and it is large if the direction is “antiparallel”.
The foregoing is explained below more specifically with reference to FIG. 13. A tunnel current supplied from the bit line 11 flows through the magnetization free layer (memory layer) 2, the tunnel barrier layer 3, and the magnetization pinned layer 4. Reading current, which varies depending on the resistance to the tunnel current, is led out of the leading electrode layer 6. Thus, the magnitude of the reading current indicates the direction of magnetic spin of the magnetization free layer (memory layer) 2.
In other words, if the directions of magnetization of the magnetization free layer (memory layer) 2 and the magnetization pinned layer 4 are “parallel” to each other and hence the magnetic spins are aligned as shown in the left side of FIG. 13, then resistance between the two layers is small and a large reading current flows through the tunnel barrier layer 3. By contrast, if the directions of magnetization of the magnetization free layer (memory layer) 2 and the magnetization pinned layer 4 are “antiparallel” to each other and hence the magnetic spins are opposite as shown in the right side of FIG. 13, then resistance between the two layers is large and a small reading current flows through the tunnel barrier layer 3.
As shown in FIG. 10, the leading electrode layer 6 of the TMR element 10 is connected to the drain electrode 23 of the transistor 15 for reading through the leading wiring 7, the reading connecting plugs 30 and 32, and the reading landing pads 31 and 32. The source electrode 27 of the reading transistor 15 is connected to the sense line 14. Therefore, at the time of MRAM reading, one TMR element 10 is selected by control signals to the gate electrode (reading word line) 13 from the TMR elements 10 which are connected to the bit line 11 to which the drive current is applied. The reading current of the selected TMR element 10 is output to the sense line 14 through the field effect transistor 15 for reading. In this way the field effect transistor 15 functions as a switching element to selectively read information stored in the TMR element 10.
Incidentally, the transistor 15 may be an n-type or p-type field effect transistor; however, it may be replaced by any switching element such as diode, bipolar transistor, and MESFET (Metal Semiconductor Field Effect Transistor).
FIG. 14 a plan view showing the arrangement of a 1M bit MRAM. It is to be noted that a large number of memory cells are concentratedly formed in the memory part, and peripheral circuits such as control circuits are formed around the memory part.
FIG. 15 is a plan view showing an example of the memory cell arrangement in MRAM of related art (refer to Patent Document 1: U.S. Pat. No. 6,174,737, specification pp. 2-6, FIGS. 1 to 13). In the case of MRAM shown, two bilaterally symmetrical memory cells are paired, and one pair is a unit of the large number of memory cells. One memory cell includes one TMR element 10 and one transistor for reading (selection). It is a memory cell of 1T1J type. It also includes the lead wiring 7 extending from the leading electrode 6 of the TMR element 10 and the reading connecting plug 30 which connects the lead wiring 7 to the drain electrode of the transistor for reading (selection). There are also the bit lines 11 and the writing word lines 12 connected to memory cells. For brevity, lower wirings and transistors for reading (selection) are not shown.
FIG. 16 is a schematic sectional view showing the arrangement of four memory cells of the MRAM mentioned above. One memory cell is essentially identical in structure with that shown in FIG. 10. That is, in the upper part of the memory cell are arranged the TMR element 10 (mentioned above), the bit line 11, and the writing word line 12. The bit line 11 is formed above the TMR element 10 so that it is electrically connected to the top coat layer 1 of the TMR element 10, and the writing word line 12 is formed under the TMR element 10, with an insulating layer interposed between them. In the lower part of the memory cell is the p-type well region 21 formed in the p-type silicon semiconductor substrate 20. In the p-type well region 21 is the n-type MOS field effect transistor 15 for section which includes the drain electrode 23, the drain region 24, the gate electrode 13, the gate insulating film 25, the source region 26, and the source electrode 27. The gate electrode 13 of the transistor 15 is a long narrow strip which connects cells, and it functions also as the read word line 13. The drain electrode 23 is connected to the leading electrode layer 6 of the TMR element 10 through the lead wiring 7, the reading connecting plugs 30, 32, and 34, and the reading landing pads 31, 33, and 35. The source electrode 27 is connected to the sense line 14. The source region 26, the source electrode 27, and the sense line 14 are shared by the bilaterally symmetrical two memory cells.
The memory part of the MRAM shown in FIGS. 15 and 16 is produced by the process outlined in the following.
The process starts with forming the MOS field effect transistors 15 for reading and the oxide films 22, such as STI (Shallow Trench Isolation) and LOCOS (Local Oxidation of Silicon), to separate the transistors 15, in the p-type well region 21 of the silicon substrate 20 by using the known semiconductor technology.
In the next step, the insulating film and lower wiring are formed. The writing word line 12 and the reading landing pad 31 are formed in the following manner. A silicon oxide film as the interlayer insulating film is deposited by CVD (Chemical Vapor Deposition) method. The interlayer insulating film is patterned by photolithography and dry etching. A thin film (not shown) of tantalum or tantalum nitride as the barrier layer is formed by sputtering over the entire surface of the interlayer insulating film. Wiring grooves and openings are filled with copper by CVD method or plating method. The surface is planarized by CMP (chemical-mechanical polishing). In this way, the writing word line 12 and the reading landing pad 31 are formed. The sense line 14 is formed in the following manner. An aluminum thin film is formed by sputtering or vapor deposition. Then, it is patterned by photolithography and dry etching. In this way, the aluminum wiring is formed.
FIGS. 17 and 18 are schematic sectional views showing the flow of steps for fabricating the upper structures, such as TMR element 10, on the lower wiring layer which has been formed as mentioned above. The position of constituents in these sectional views is identical with that shown in FIG. 16; therefore, for brevity, these sectional views only show the upper part above the interlayer insulating film on which the writing word line 12 and the reading landing pad 31 are formed.
A silicon nitride film (not shown) to prevent diffusion of copper ions is formed by CVD method. As shown in FIG. 17A, the interlayer insulating film 50 which is a silicon oxide film is deposited by CVD method and then it is patterned by photolithography and dry etching to form the openings 51.
As shown in FIG. 17B, a thin film of titanium nitride as the barrier layer (not shown) is formed by sputtering over the entire surface of the interlayer insulating film 50. The openings 51 are filled with tungsten or the like by CVD method. The surface is planarized by CMP method. In this way the connecting plugs 30 (or tungsten plugs) for reading are formed.
As shown in FIG. 17C, the following layers are sequentially formed by sputtering over the entire surface. A tantalum layer which becomes the leading electrode layer 6 and the lead wiring 7. A layer of manganese alloy of platinum which becomes the antiferromagnetic layer 5. A layer of iron-cobalt alloy which becomes the magnetization pinned layer 4. An aluminum oxide layer which becomes the tunnel barrier layer 3. A layer of CoFe-30B (iron-cobalt-boron alloy) which becomes the magnetization free layer 2. A layer of thallium which becomes the top coat layer 1. In this way the layers constituting the TMR element 10 are formed. Incidentally, the tunnel barrier layer 3 is formed by oxidizing or nitriding the metal film formed by sputtering.
As shown in FIG. 17D, a positive-type resist layer 52 is formed on the surface by coating. The resist layer 52 is exposed through the photomask 55 which has an exposure pattern corresponding to the shape of the TMR element. Exposure is followed by development. In this way there is obtained the resist mask 56 which has been patterned in the shape of the TMR element. As mentioned later, the exposure pattern 53 may be deformed due to proximity effect if the patterns of TMR element are close to each other. As the result, it is impossible to form the resist mask 56 which is correctly patterned in the shape of the TMR element.
As shown in FIG. 18A, dry etching is performed through the resist mask 56 to form the top coat layer 1 conforming to the shape of the TMR element.
Next, the resist mask 56 is removed. As shown in FIG. 18B, etching is performed through the top coat layer 1 on the memory layer 2, the tunnel barrier layer 3, the magnetization pinned layer 4, and the antiferromagnetic layer 5, so that they conform to the shape of the TMR element 10.
As shown in FIG. 18C, the resist mask 57 is formed by photolithography. Etching is performed on the leading electrode layer 6 to form the leading electrode layer 6 and the lead wiring 7 of the TMR element 10. The resist mask 57 is removed.
Although not shown, a silicon oxide film, as the interlayer insulating film 54, is deposited by CVD method, so that the TMR element 10 and the lead wiring 7 are embedded. Subsequently, the bit lines 11 of copper or aluminum are formed by the above-mentioned method. Finally, the protective layer is formed on the top surface.
In the foregoing example, the lead wiring 7 is connected to the reading landing pad 31 through the reading connecting plug 30. However, this structure may be modified such that the step of forming the reading connecting plug 30 shown in FIG. 17B is omitted and the lead wiring 7 is formed directly on the opening 51.
In any way, connecting holes are necessary for connection of the TMR element 10 to the nearby reading transistor 15. On the other hand, usually the periphery of the connecting holes is not flat, and this disturbs the flatness of the TMR element 10. Therefore, in order to form the TMR element 10 with a flat surface, it is desirable that all the connecting holes around the TMR element 10 be arranged uniformly and remotely, instead of connecting holes such as specific reading connecting plug 30 being formed near the TMR element 10.